UART Protocol Analyzer (PGY-UART-EX-PD) are the Protocol Analyzers with multiple features to capture and debug communication between host and design under test. PGY-UART-EX-PD is the leading instrument that enables the design and test engineers to test the respective UART designs for its specifications by configuring the PGY-UART-EX-PD as Master/Slave, generating UART traffic and decoding the UART protocol decode packets.
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UART stands for Universal Asynchronous Receiver Transmitter. A UART’s main purpose is to transmit and receive serial data. PGY-UART-EX-PD is the leading instrument that enables the design and test engineers to test the UART designs for its specifications. Generating UART traffic with custom traffic capability and decoding UART Protocol packets.
Features
- Supports custom UART traffic generation
- Simultaneously generate UART traffic and Protocol decode of the bus
- Variable UART baud rates
- Continuous streaming of protocol data to host computer to provides large buffer
- Timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Multi Domain View
Multi domain View provides the complete view of UART Protocol activity in single GUI. User can easily setup the analyzer to generate UART traffic using a GUI or script. User can capture Protocol activity at specific event and decode the transition on UART line. The decoded results can be viewed in timing diagram and Protocol listing window with auto–correlation. This comprehensive view of information makes it industry best, offering an easy to use solution to debug the UART protocol activity.
Exerciser
PGY–UART–EX–PD supports UART traffic generation using GUI and Script. User can generate simple traffic generation using the GUI to test the DUT. Script based GUI provides flexibility to emulate the complete expected traffic in real world including error injections. In this sample script user can generate UART traffic
Timing Diagram and Protocol Listing View
Timing view provides the plot of TX signals with bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in timing diagram for any timing errors.
Protocol window provides the decoded packet information in each state and all packet details with error info in packet. Selected frame in Protocol listing window will be auto correlated in timing view to view the timing information of the packet.
Setup View
Users can configure the PGY-UART-EX-PD for different baud rates, for different configurations of Data width and Stop bits. Users can also choose whether the parity is odd or even depending on the data type being used and also select the data shift type.
UART Specifications
